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esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 1 / 15 revision history : revision 1.0 (jul. 06, 2007) - original
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 2 / 15 psram 16-mbit (1m x 16) pseudo static ram features features ?wide voltage range: 1.7v?1.95v ?access time: 70 ns ?ultra-low active power ? typical active current: 3 ma @ f = 1 mhz ? typical active current: 18 ma @ f = fmax ?ultra low standby power ?automatic power-down when deselected ?cmos for optimum speed/power ?deep sleep mode ?available in lead-free 48-ball bga package ?operating temperature: ?40c to +85c functional description[1] the m24d16161za is a high-performance cmos pseudo static ram organized as 1m words by 16 bits that supports an asynchronous memory interf ace. this device features advanced circuit design to provide ultra-low active current. this is ideal for portable applications such as cellular telephones. the device can be put into standby mode when deselected ( ce high or both bhe and ble are high). the input/output pins (i/o0through i/o 15 ) are placed in a high-impedance state when: deselected ( ce high), outputs are disabled ( oe high), both byte high enable and byte low enable are disabled ( bhe , ble high), or during a write operation ( ce low and we low). to write to the device, take chip enable ( ce low) and write enable ( we ) input low. if byte low enable ( ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 19 ). if byte high enable ( bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the lo cation specified on the address pins (a 0 through a 19 ).to read from the device, take chip enables ( ce low) and output enable ( oe ) low while forcing the write enable ( we ) high. if byte low enable ( ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable ( bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . refer to the truth table for a complete description of read and write modes. deep sleep mode is enabled by driving zz low. see the truth table for a complete description of read, write, and deep sleep mode. logic block diagram
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 3 / 15 pin configuration[2, 3] 48-ball vfbga top view product portfolio power dissipation operating i cc (ma) v cc range (v) f = 1mhz f = f max standby i sb2 (a) product min. typ. max. speed(ns) typ.[4] max. typ.[4] max. typ. [4] max. m24d16161za 1.7 1.8 1.95 70 3 5 18 20 55 70 low-power modes at power-up, all four sections of the die are activated and the psram enters into its default state of full memory size and refresh space. this device prov ides four different low-power modes. 1.reduced memory size operation 2.partial array refresh 3.deep sleep mode 4.temperature controlled refresh reduced memory size operation in this mode, the 16 mb psram can be operated as a 12-mbit,8-mbit or a 4-mbit memory block. please refer to ?variable address space register (var)? on page4 for the protocol to turn on/off sectio ns of the memory. the device remains in rms mode until changes to the variable address space register are made to revert back to a complete 16-mbit psram. partial array refresh the partial array refresh mode allows customers to turn off sections of the memory blo ck in the stand-by mode (with zz tied low) to reduce standby current. in this mode the psram will only refresh certain portions of the memory in the stand-by mode, as configured by the user through the settings in the variable address register. once zz returns high in this mode, the psram goes back too perating in full address refresh. please refer to ?variable address space register (var)? on page4 for the protocol to turn off sections of the memory in stand-by mode. if the var register is not updated after the power up, the psram will be in its default state. in the default state the whole memory array will be refreshed in the stand-by mode. the 16-mbit is divided into four 4-mbit sections allowing certain sections to be active (i.e., refreshed). deep sleep mode in this mode, the data integrity in the psram is not guaranteed. this mode can be used to lower the power consumption of the psram in an application. this mode can be enabled and disabled through var similar to the rms and par mode. deep sleep mode is activated by driving zz low. the device stays in the deep sleep mode until zz is driven high. notes: 2.ball h6, e3 can be used to upgrade to 32m and 64m density respectively. 3.nc ?no connect? - not connec ted internally to the die. 4.typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25c. tested initially and after any desig n changes that may affect the parameter.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 4 / 15 variable address mode register (var) update[5, 6] deep sleep mode?entry/exit [7] var update and deep sleep mode timing[5, 6] parameter description min. max. unit t zzwe zz low to write start 1 s t cdr chip deselect to zz low 0 ns t r [7] operation recovery time (deep sleep mode only) 200 s t zzmin deep sleep mode time 8 s notes: 5. oe and the data pins are in a don?t care state while the device is in variable address mode. 6.all other timing parameters are as shown in the data sheets. 7.t r applies only in the deep sleep mode.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 5 / 15 variable address space register (var) variable address space?address patterns partial array refresh m ode (a3 = 0, a4 = 1) a2 a1,a0 refresh section address size density 0 1 1 1/4 th of the array 00000h-3ffffh (a19 = a18 = 0) 256k x 16 4m 0 1 0 1/2 th of the array 00000h-7ffff h (a19 = 0) 512k x 16 8m 0 0 1 3/4 th of the array 00000h-bffffh (a19: a18 not equal to 1 1) 768k x 16 12m 1 1 1 1/4 th of the array c0000h-fffffh (a19 = a18= 1) 256k x 16 4m 1 1 0 1/2 th of the array 80000h-fffffh (a19 = 1) 512k x 16 8m 1 0 1 3/4 th of the array 40000h-fffffh (a19:a 18 not equal to 0 0) 768k x 16 12m reduced memory size mode (a3 = 1, a4 = 1) 0 1 1 1/4 th of the array 00000h-3ffffh (a19 = a18 = 0) 256k x 16 4m 0 1 0 1/2 th of the array 00000h-7ffffh (a19 = 0) 512k x 16 8m 0 0 1 3/4 th of the array 00000h-bffffh (a19: a18 not equal to 1 1) 768k x 16 12m 0 0 0 full array 00000h-fffffh (default) 1m x 16 16m 1 1 1 1/4 th of the array c0000h-fffffh (a19 = a18 = 1) 256k x 16 4m 1 1 0 1/2 th of the array 80000h-fffffh (a19 = 1) 512k x 16 8m 1 0 1 3/4 th of the array 40000h-fffffh (a19:a 18 not equal to 0 0) 768k x 16 12m 1 0 0 full array 00000h-fffffh (default) 1m x 16 16m
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 6 / 15 power-up characteristics the initialization sequence is shown in the figure below. chip select ( ce ) should be high for at least 200 s after v cc has reached a stable value. no access must be attempted during this period of 200 s. the state of zz has to be high (h) for the duration of power-up. parameter description min. typ. max. unit tpu chip enable low after stable v cc 200 s
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 7 / 15 maximum ratings (above which the useful life may be impaired. for user guide-lines, not tested.) storage temperature .............. ................ ...?65c to +150c ambient temperature with power applied........... .............. ................ ....?55c to +125c supply voltage to ground potential.?0.2v to v ccmax + 0.3v dc voltage applied to outputs in high z state[8, 9, 10]......................?0.2v to v ccmax + 0.3v dc input voltage[8, 9, 10]............. .....?0.2v to v ccmax + 0.3v output current into outputs (l ow).............................20 ma static discharge voltage......... ................ ............... .. > 2001v (per mil-std-883, method 3015) latch-up current............ ................. ............ ...........> 200 ma operating range range operating temperature (t a ) v cc industrial ? 40c to +85c 1.7v to 1.95v dc electrical characteristics (over the operating range) [8, 9, 10] -70 parameter description test conditions min. typ.[4] max. unit v cc supply voltage 1.7 1.8 1.95 v v oh output high voltage i oh = ? 0.1 ma v cc =1.7v to 1.95v v cc -0.2 v v ol output low voltage i ol = 0.1 ma v cc =1.7v to 1.95v 0.2 v v ih input high voltage 1.7v v cc 1.95 0.8* v cc v cc +0.3 v v il input low voltage v cc = 1.7v to 1.95v -0.2 0.2* v cc v i ix input leakage current gnd v in v cc -1 +1 a i oz output leakage current gnd v out v cc -1 +1 a f = f max = 1/t rc v cc = v ccmax i out = 0ma cmos levels 18 20 ma i cc v cc operating supply current f = 1 mhz 3 5 ma i sb1 automatic ce power-down current ?cmos inputs ce > v cc ? 0.2v, v in > v cc ? 0.2v, v in < 0.2v, f = f max (address and data only), f = 0 ( oe , we , bhe and ble ), v cc = 1.95v, zz v cc ? 0.2v 55 70 a i sb2 automatic ce power-down current ?cmos inputs ce v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0, v cc = v ccmax zz v cc ? 0.2v 55 70 a i zz deep sleep current v cc = v ccmax , zz 0.2v, ce = high or bhe and ble = high 10 a capacitance[11] parameter description test conditions max. unit c in input capacitance 8 pf c out output capacitance ta = 25c, f = 1 mhz v cc = v cc(typ) 8 pf notes: 8.v il(min) = ?0.5v for pulse durations less than 20 ns. 9.v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 10.overshoot and undershoot specifications are characterized and are not 100% tested. 11.tested initially and after any design or process changes that may affect these parameters.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 8 / 15 thermal resistance[11] parameter description test conditions bga unit ja thermal resistance(junction to ambient) 56 c/w jc thermal resistance (junction to case) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/ jesd51. 11 c/w ac test loads and waveforms parameters 1.8v (v cc ) unit r1 14000 ? r2 14000 ? r th 7000 ? v th 0.9 v
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 9 / 15 switching characteristics over the operating range [12, 13, 14, 15, 18] -70 parameter description min. max. unit read cycle t rc [17] read cycle time 70 40000 ns t cd chip deselect time ce , ble / bhe high pulse time 15 ns t aa address to data valid 70 ns t oha data hold from address change 10 ns t ace ce low to data valid 70 ns t doe oe low to data valid 35 ns t lzoe oe low to low z [13, 14, 16] 5 ns t hzoe oe high to high z [13, 14, 16] 25 ns t lzce ce low low z [13, 14, 16] 10 ns t hzce ce high to high z [13, 14, 16] 25 ns t dbe ble / bhe low to data valid 70 ns t lzbe ble / bhe low to low z[13, 14, 16] 5 ns t hzbe ble / bhe high to high z[13, 14, 16] 25 ns write cycle[15] t wc write cycle time 70 40000 ns t sce ce low to write end 60 ns t aw chip deselect time ce , ble / bhe high pulse time 15 ns t ha address hold from write end 60 ns t sa address set-up to write start 0 ns t pwe we pulse width 0 ns t bw ble / bhe low to write end 50 ns t sd data set-up to write end 60 ns t hd data hold from write end 25 ns t hzwe we low to high-z[13, 14, 16] 0 25 ns t lzwe we high to low-z[13, 14, 16] 10 ns notes: 12. test conditions for all parameters other than tri-state para meters assume signal transition time of 1 ns/v, timing referenc e levels of v cc /2, input pulse levels of 0v to v cc , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 13. at any given temperature and voltage conditions t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. all low-z parameters will be measured with a load capacitance of 30 pf (1.8v). 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the out puts enter a high-impedance state. 15. the internal write time of the me mory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and an y of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the e dge of the signal that terminates the write. 16. high-z and low-z parameters are characterized and are not 100% tested. 17. if invalid address signals shorter than min. t rc are continuously repeated for 40 s, the device needs a normal read timing (t rc ) or needs to enter standby state at least once in every 40 s. 18. in order to achieve 70 ns pe rformance, the read access must be ce controlled. that is, the addresses must be stable prior to ce going active.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 10 / 15 switching waveforms read cycle 1 (address transition controlled)[20, 21] read cycle 2 ( oe controlled)[19, 21] notes: 19.whenever ce , bhe / ble are taken inactive, they must remain inactive for a minimum of 15 ns. 20.device is continuously selected. oe , ce = v il . 21. we is high for read cycle.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 11 / 15 switching waveforms (continued) write cycle 1 ( we controlled) [15, 16, 19, 22, 23] notes: 22.data i/o is high-impedance if oe v ih . 23.during the don?t care period in the data i/o waveform, the i/os are in out put state and input signals should not be applied.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 12 / 15 write cycle 2 ( ce controlled) [15, 16, 19, 22, 23] write cycle 3 ( we controlled, oe low)[ 19, 23]
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 13 / 15 switching waveforms (continued) write cycle 4 ( bhe / ble controlled, oe low)[15, 19, 22, 23] truth table[24, 25] zz ce we oe bhe ble inputs/outputs mode power h h x x x x high z deselect/power-down standby (i sb ) h x x x h h high z deselect/power-down standby (i sb ) h l x x h h high z deselect/power-down standby (i sb ) h l h l l l data out (i/o 0 -i/o 15 ) read active (i cc ) h l h l h l data out (i/o 0 -i/o 7 ); i/o 8 -i/o 15 in high z read active (i cc ) h l h l l h data out (i/o 8 -i/o 15 ); i/o 0 -i/o 7 in high z read active (i cc ) h l h h l l high z output disabled active (i cc ) h l h h h l high z output disabled active (i cc ) h l h h l h high z output disabled active (i cc ) h l l x l l data in (i/o 0 -i/o 15 ) write (upper byte and lower byte active (i cc ) h l l x h l data in (i/o 0 -i/o 7 ); i/o 8 -i/o 15 in high z write (lower byte only) active (i cc ) h l l x l h data in (i/o 8 -i/o 15 ); i/o 0 -i/o 7 in high z write (upper byte only) active (i cc ) l h x x h h data in (a 0 -a 4 ) write (variable address mode register) active (i cc ) l h x x x x high z deep power-down/par deep sleep (i zz )/stand by notes: 24.h = logic high, l = logic low, x = don?t care. 25.during zz = l and ce = h, mode depends on how the var is set up either in par or deep sleep modes.
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 14 / 15 ordering information speed (ns) ordering code package type operating range 70 M24D16161ZA-70BIG 48-ball fine pitch vfbga (6 mm 8 mm 1 mm) lead-free industrial package diagram 48-lead vfbga (6 x 8 x 1 mm)
esmt m24d16161za elite semiconductor memory technology inc. publication date : jul. 2007 revision : 1.0 15 / 15 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. the information contained h erein is presented only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, co pyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inher ently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer w hen making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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